1. Field of the Invention
The present invention relates to a DC offset cancellation circuit and a programmable gain amplifier using the same. More particularly, the present invention relates to a DC offset cancellation circuit having a DC offset cancellation resistor connected between an inverse terminal and a non-inverse terminal of an operational amplifier, and a programmable gain amplifier (PGA) using the same.
2. Description of the Related Art
In general, an operational amplifier is considered ideal when it has an input voltage of “0” and an output voltage of “0.” However, actually, the operational amplifier (OP-Amp) has a moderate output voltage, i.e., an offset voltage even at an input voltage of “0.” This direct current (DC) offset occurs due to an internal structure of the operational amplifier. Accordingly, the operational amplifier may be equipped with an offset adjuster for adjusting the DC offset so that the output voltage is “0” at the input voltage of “0.” The direct current (DC) offset, if present, may adversely affect processing of a normal signal source. Thus, existence of the DC offset is most decisive factor of performance in wireless telecommunication devices.
Especially, an analogue signal inputted to an alternating current (A/D) converter of a chaotic RF transceiver is highly susceptible to the DC offset, which thus should be necessarily eliminated.
FIG. 1 is a block diagram partially illustrating a receiver of a chaotic RF transceiver.
As shown in FIG. 1, a signal inputted to an A/D converter 104 is fed from an antenna through a detector 101 and a low pass filter (LPF) 102. The signal fed from the antenna and detected by the detector 101 is affected by multi-path fading or surrounding interference signals. This accordingly causes the detected signal to be non-uniform in its size and to fluctuate unstably. This influences the A/D converter 104 for converting the analogue signal into a digital pulse, rendering the signal hardly discernable. Therefore, the detected signal, before being inputted to the A/D converter, should be processed to have a constant size. This function is executed by a programmable gain amplifier 103.
FIG. 2 is a block diagram illustrating a conventional programmable gain amplifier (PGA).
The PGA shown in FIG. 2 includes three operational amplifiers 201, 202 and 203. The first operational amplifier 201 has an inverse terminal to which a detected signal is inputted through resistors 221 and 222. An output from the operational amplifier 201 is fed back to the inverse terminal of the first operational amplifier 201 through the resistor 223 and the capacitor 231. The inverse terminal of the first operational amplifier 201 has an input resistance varied by a switch 211 which switches on/off in response to a digital control signal, thereby controlling gain of the first operational amplifier 201.
The second operational amplifier 202 has an inverse terminal to which the output of the first operational amplifier 201 is inputted through resistors 224, 225, and 226. An output from the second operational amplifier 202 is fed back to the inverse terminal of the second operational amplifier 202 through a resistor 227 and a capacitor 232. The inverse terminal of the second operational amplifier 202 has an input resistance varied by switches 212 and 213 which switch on/off in response to a digital control signal, thereby controlling gain of the second operational amplifier 202.
The switch is operated in response to a 3-bit digital control signal to control gain of the first and second operational amplifiers 201 and 202. This keeps total gain of the PGA constant. The capacitors 231 and 232 may be optionally adopted to serve as a low pass filter (LPF) that feeds back only a signal of a low frequency bandwidth.
The third operational amplifier 203 has an inverse terminal to which the output of the second operational amplifier 202 is inputted through a resistor 228. An output of the third operational amplifier 203 is filtered by the LPF including the resistor 229 and the capacitor 233, and then fed back to the non-inverse terminal. The output of the third operational amplifier 202 is inputted to the inverse terminal of the first operational amplifier 201 through a resistor 230.
In the conventional PGA, DC offset is cancelled as follows.
Out of PGA outputs from the second operational amplifier 203, a low frequency component is fed back to an input of the PGA. In this process, the PGA output of the low frequency component is filtered by the low pass filter including the resistor 229 and the capacitor 233, i.e., a feedback circuit of the third operational amplifier 203, and then inputted to the first operational amplifier 201, thereby preventing a DC component from being output.
In the conventional PGA, a feedback process is compulsory for DC cancellation, thus necessitating an additional operational amplifier and accessory devices. This consumes considerable power, accordingly not suitable for use in mobile telecommunication devices running on battery power. Also, the third operational amplifier 203 used in the feedback is a non-ideal operational amplifier which requires DC offset cancellation. Thus, the third operational amplifier 203 normally acts as the LPF only when a separate DC voltage corresponding to the DC offset is applied. Moreover, the conventional PGA, when configured in an integrated circuit, requires a pad that occupies a relatively large space. Besides, the conventional operational amplifier should be optimized to match a circuit for varying a voltage outside the integrated circuit.